Semiconductor circuit and electronic apparatus

ABSTRACT

A semiconductor circuit according to the present disclosure includes: a first memory element including a first terminal, a second terminal coupled to a first node, and a tunnel barrier film, and configured to store information by breaking the tunnel barrier film; a first transistor including a drain coupled to the first node, a source, a gate, and a back gate coupled to a second node; and a second transistor including a drain, a source coupled to the second node, and a gate coupled to the first node.

TECHNICAL FIELD

The present disclosure relates to a semiconductor circuit configured tostore information and an electronic apparatus that includes thesemiconductor circuit.

BACKGROUND ART

A semiconductor circuit often includes a so-called OTP (One TimeProgrammable) memory configured to write information once. PatentLiterature 1 discloses a technique that structures the OTP memory usinga magnetic tunnel junction (MTJ: Magnetic Tunnel Junction) device.

CITATION LIST Patent Literature

-   Patent Literature 1: Japanese Unexamined Patent Application    Publication No. 2010-225259

SUMMARY OF THE INVENTION

Incidentally, in an OTP memory, it is desired that a size of a memorycell is small, and a further reduction of the size is expected.

It is desirable to provide a semiconductor circuit and an electronicapparatus that make it possible to reduce a size of a memory cell.

A semiconductor circuit according to one embodiment of the presentdisclosure includes a first memory element, a first transistor, and asecond transistor. The first memory element includes a first terminal, asecond terminal coupled to a first node, and a tunnel barrier film, andis configured to store information by breaking the tunnel barrier film.The first transistor includes a drain coupled to the first node, asource, a gate, and a back gate coupled to a second node. The secondtransistor includes a drain, a source coupled to the second node, and agate coupled to the first node.

An electronic apparatus according to one embodiment of the presentdisclosure includes a first memory element, a first transistor, a secondtransistor, and a processing circuit. The first memory element includesa first terminal, a second terminal coupled to a first node, and atunnel barrier film, and is configured to store information by breakingthe tunnel barrier film. The first transistor includes a drain coupledto the first node, a source, a gate, and a back gate coupled to a secondnode. The second transistor includes a drain, a source coupled to thesecond node, and a gate coupled to the first node. The processingcircuit is configured to perform a process, on the basis of theinformation stored in the first memory element.

The semiconductor circuit or the electronic apparatus according to oneembodiment of the present disclosure includes the first memory elementhaving the tunnel barrier film and configured to store the informationby breaking the tunnel barrier film. The second terminal of the firstmemory element is coupled to the first node. The drain of the firsttransistor is coupled to the first node, and the back gate of the firsttransistor is coupled to the second node. The gate of the secondtransistor is coupled to the first node, and the source of the secondtransistor is couped to the second node.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a configuration example of asemiconductor circuit according to an embodiment of the presentdisclosure.

FIG. 2 is a block diagram illustrating a configuration example of amemory circuit illustrated in FIG. 1.

FIG. 3 is a circuit diagram illustrating a configuration example of thememory circuit illustrated in FIG. 2.

FIG. 4 is a schematic cross-sectional diagram illustrating aconfiguration example of a memory cell array illustrated in FIG. 3.

FIG. 5 is an explanatory diagram illustrating an example of a writeoperation in the memory circuit illustrated in FIG. 2.

FIG. 6 is an explanatory diagram illustrating an example of a readoperation in the memory circuit illustrated in FIG. 2.

FIG. 7 is a circuit diagram illustrating a configuration example of amemory circuit according to a modification example.

FIG. 8 is a circuit diagram illustrating a configuration example of amemory circuit according to another modification example.

FIG. 9 is an explanatory diagram illustrating an example of the writeoperation in the memory circuit illustrated in FIG. 8.

FIG. 10 is an explanatory diagram illustrating an example of the readoperation in the memory circuit illustrated in FIG. 8.

FIG. 11 is a circuit diagram illustrating a configuration example of amemory circuit according to another modification example.

FIG. 12 is a block diagram illustrating a configuration example of amemory circuit according to another modification example.

FIG. 13 is a circuit diagram illustrating a configuration example of thememory circuit illustrated in FIG. 12.

FIG. 14 is an explanatory diagram illustrating an example of the writeoperation in the memory circuit illustrated in FIG. 13.

FIG. 15 is an explanatory diagram illustrating an example of the readoperation in the memory circuit illustrated in FIG. 13.

FIG. 16 is a circuit diagram illustrating a configuration example of amemory circuit according to another modification example.

FIG. 17 is a perspective diagram illustrating an external appearanceconfiguration of a smartphone to which an embodiment is applied.

MODES FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present disclosure will be described indetail with reference to the drawings. Note that the description will bemade in the following order.

1. Embodiment 2. Application Example 1. Embodiment Configuration Example

FIG. 1 illustrates a configuration example of a semiconductor circuit (asemiconductor circuit 1) according to an embodiment. The semiconductorcircuit 1 is configured to operate on the basis of stored information.The semiconductor circuit 1 is formed on one semiconductor chip in thisexample. The semiconductor circuit 1 includes a processing circuit 11, amemory circuit 12, and a memory circuit 20.

The processing circuit 11 includes, for example, a digital circuit andan analog circuit, and is configured to perform a predetermined process.The processing circuit 11 performs a process using, for example,information stored in the memory circuits 12 and 20.

The memory circuit 12 is a nonvolatile memory configured to storeinformation and rewrite the information. The memory circuit 12 has aplurality of memory cells. The memory cells each have a memory elementM. In this example, the memory element M is a spin transfer torque (STT:Spin Transfer Torque) magnetic tunnel junction element in whichinformation is stored by changing an orientation of a magnetization of afree layer F (described later) by spin injection. The memory element Mincludes a free layer F, a tunnel barrier layer T, and a pinned layer P.The pinned layer P includes a ferromagnetic material whose direction ofthe magnetization is fixed in, for example, a film surface perpendiculardirection. The free layer F includes a ferromagnetic material whosedirection of the magnetization changes, for example, in the film surfaceperpendicular direction, in response to a spin-polarized current flowingthereto. The tunnel barrier layer T is configured to break a magneticcoupling between the pinned layer P and the free layer F and to allow atunnel current to flow. The tunnel barrier layer T includes a materialsuch as magnesium oxide (MgO), for example. It should be noted that itis not limited thereto, and, for example, alumina may be usedalternatively.

The memory circuit 12 writes information to the memory element M bycausing a current to flow to the memory element M and setting thedirection of the magnetization in the free layer F of the memory elementM. In the memory element M, a resistance value between terminals changesin accordance with the direction of the magnetization in the free layerF. In the memory circuit 12, the memory element M may take tworesistance states RL and RH that are distinguishable from each other.The resistance state RH is a state in which the resistance value is highand the resistance state RL is a state in which the resistance value islow. The resistance value in the resistance state RL is, for example,about 10 kΩ.

The memory circuit 20 is a so-called OTP memory configured to storeinformation and write information once.

FIG. 2 illustrates a configuration example of the memory circuit 20. Thememory circuit 20 has a plurality of memory cell arrays MA (32 memorycell arrays MA[0], MA[1], . . . , MA[31], in this example), a pluralityof reader writers IO (32 reader writers IO[0], IO[1], . . . , IO[31], inthis example), a word line driver 21, and a controller 22.

The plurality of memory cell arrays MA is respectively providedcorresponding to the plurality of reader writers IO. Each of theplurality of memory cell arrays MA has a plurality of memory cells MCdisposed in a matrix.

FIG. 3 illustrates a configuration example of the memory cell array MA.The memory cell array MA has a plurality of word lines WL, a pluralityof bit lines BL, a plurality of source lines SL, and a voltage line VL.The word lines WL are provided to extend in a row direction (a lateraldirection in FIG. 3), and are coupled to the word line driver 21. Asillustrated in FIG. 2, the word lines WL are so provided as to crossover the plurality of memory cell arrays MA[0] to MA[31]. The bit linesBL are provided to extend in a column direction (a vertical direction inFIG. 3), and are coupled to the reader writer IO. The source lines SLare provided to extend in the column direction. The source lines SL aregrounded in this example. The voltage line VL is provided to extend inthe column direction, and is coupled to the reader writer IO. The memorycell array MA has the plurality of memory cells MC and a plurality oftransistors TRA.

Each of the plurality of memory cells MC includes the memory element Mand a transistor TRC.

The memory element M includes the free layer F, the tunnel barrier layerT, and the pinned layer P. That is, the memory element M of the memorycircuit 20 has the same configuration as the memory element M of thememory circuit 12. In the memory cell MC, information is stored bybreaking the tunnel barrier layer T of the memory element M.Specifically, a resistance value of the memory element M is reduced as aresult of the breakage of the tunnel barrier layer T as with a so-calledanti-fuse. In the memory circuit 20, the memory element M may take tworesistance states RL and RS that are distinguishable from each other.The resistance state RS is a resistance state following a short-circuitbreakage. The resistance value in the resistance state RS is lower thanthe resistance value in the resistance state RL. One end of the memoryelement M is coupled to the bit line BL and the other end is coupled toa node N1. In this example, the free layer F of the memory element M iscoupled to the bit line BL and the pinned layer P is coupled to the nodeN1. It should be noted that it is not limited thereto. Alternatively,for example, the pinned layer P may be coupled to the bit line BL andthe free layer F may be coupled to the node N1.

The transistor TRC is an N-type MOS (Metal Oxide Semiconductor)transistor, a drain of which is coupled to the node N1, a source ofwhich is coupled to the source line SL, a gate of which is coupled tothe word line WL, and a back gate of which is coupled to a node N2. Thenodes N2 of the memory cells MC corresponding to one row that areprovided side by side in the row direction (the lateral direction inFIG. 3) are coupled to each other. Specifically, the transistors TRC (atransistor group 100 in FIG. 3) of the memory cells MC corresponding toone row are formed on one P-type well (P-well).

FIG. 4 illustrates a configuration example of the transistor group 100.In this example, an N-type region 101N is formed on a P-typesemiconductor substrate 100P, and a P-well 102P is formed in the N-typeregion 101N. The semiconductor substrate 100P and the P-well 102P areelectrically insulated from each other by the N-type region 101N. Thetransistors TRC of the memory cells MC corresponding to one row areformed on the P-well 102P. Thus, the back gates of the transistors TRCare electrically coupled to each other.

Note that although the transistors TRC of the memory cells MCcorresponding to one row are formed on one P-well in this example, it isnot limited thereto. The plurality of transistors TRC may berespectively formed on the plurality of P-wells.

In addition, as illustrated in FIG. 3, the nodes N1 of the memory cellsMC corresponding to one row that are disposed side by side in the rowdirection (the lateral direction in FIG. 3) are coupled to each other.

Each of the plurality of transistors TRA is an N-type MOS transistor.The plurality of transistors TRA is respectively provided correspondingto the plurality of rows of the memory cells MC. A gate of thetransistor TRA is coupled to the nodes N1 of the plurality of memorycells MC belonging to the corresponding row, a drain is coupled to thevoltage line VL, and a source is coupled to the nodes N2 of theplurality of memory cells MC belonging to the corresponding row.

The word line driver 21 (FIG. 2) is configured to select one of theplurality of word lines WL by driving the plurality of word lines WL onthe basis of a command from the controller 22.

The reader writer IO is configured to drive the plurality of bit linesBL and the voltage line VL and read information stored in the memorycell array MA on the basis of the command from the controller 22. Asillustrated in FIG. 3, the reader writer IO includes a column switch 31,a voltage generator 32, a sense amplifier 33, and a driver 34.

The column switch 31 is configured to, in a write operation, select oneof the plurality of bit lines BL and couple the selected bit line BL tothe voltage generator 32, and place other bit lines BL into a floatingstate, on the basis of the command from the controller 22. Further, thecolumn switch 31 is configured to, in a read operation, select one ofthe plurality of bit lines BL and couple the selected bit line BL to thesense amplifier 33, and place other bit lines BL into the floatingstate, on the basis of the command from the controller 22. The pluralityof column switches 31 of the plurality of reader writers IO is adaptedto select the bit lines BL that are the same as each other in number oforder, on the basis of the command from the controller 22.

The voltage generator 32 is configured to, in the write operation,generate a ground voltage or a blow voltage to be applied to theselected bit line BL, on the basis of the command from the controller22.

The sense amplifier 33 is configured to, in the read operation, generatea read voltage Vread to be applied to the selected bit line BL and readinformation stored in the memory cell MC on the basis of a currentflowing through the selected bit line BL, on the basis of the commandfrom the controller 22. The read voltage Vread may be, for example, avoltage lower than the blow voltage.

The driver 34 is configured to drive the voltage line VL, on the basisof the command from the controller 22.

The controller 22 (FIG. 2) is configured to control operations of theword line driver 21 and the plurality of reader writers 10 to writeinformation to the memory cell MC of the plurality of memory cell arraysMA, on the basis of a write command and write data supplied from theprocessing circuit 11. Further, the controller 22 is configured tocontrol operations of the word line driver 21 and the plurality ofreader writers IO to read information from the memory cell MC of theplurality of memory cell arrays MA, on the basis of a read commandsupplied from the processing circuit 11.

Here, the memory element M corresponds to one concrete example of a“first memory element” and a “second memory element” of the presentdisclosure. The tunnel barrier layer T corresponds to one concreteexample of a “tunnel barrier film” of the present disclosure. Thetransistor TRC corresponds to one concrete example of a “firsttransistor” and a “third transistor” of the present disclosure. Thetransistor TRA corresponds to one concrete example of a “secondtransistor” of the present disclosure. The node N1 corresponds to oneconcrete example of a “first node” of the present disclosure. The nodeN2 corresponds to one concrete example of a “second node” of the presentdisclosure. The word line driver 21 and the reader writer IO correspondto one concrete example of a “driver” of the present disclosure. Theword line WL corresponds to one concrete example of a “first controlline” of the present disclosure. The bit line BL corresponds to oneconcrete example of a “second control line” and a “third control line”of the present disclosure. The voltage line VL corresponds to oneconcrete example of a “fourth control line” of the present disclosure.The source line SL corresponds to one concrete example of a “fifthcontrol line” and a “sixth control line” of the present disclosure. Thememory circuit 12 corresponds to one concrete example of a “memorycircuit” of the present disclosure. The processing circuit 11corresponds to one concrete example of a “processing circuit” of thepresent disclosure.

[Operation and Working]

Next, an operation and working of the semiconductor circuit 1 of thepresent embodiment will be described.

(Outline of Overall Operation)

First, referring to FIGS. 1 to 3, an outline of an overall operation ofthe semiconductor circuit 1 will be described.

The controller 22 of the memory circuit 20 controls the operations ofthe word line driver 21 and the plurality of reader writers IO to writeinformation to the memory cell MC of the plurality of memory cell arraysMA, on the basis of the write command and the write data supplied fromthe processing circuit 11 (FIG. 1). In the write operation, the wordline driver 21 selects one of the plurality of word lines WL, on thebasis of the command from the controller 22. In each of the plurality ofreader writers the column switch 31 selects one of the plurality of bitlines BL and couples the selected bit line BL to the voltage generator32, and places other bit lines BL into the floating state, on the basisof the command from the controller 22. The voltage generator 32generates the ground voltage or the blow voltage to be applied to theselected bit line BL, on the basis of the command from the controller22. The driver 34 drives the voltage line VL, on the basis of thecommand from the controller 22. In this manner, the memory circuit 20selects the memory cell MC in each of the plurality of memory cellarrays MA by selecting the word line WL and the bit line BL, and appliesthe voltage generated by the voltage generator 32 to the selected memorycell MC. In the memory cell MC to which the blow voltage is applied, thetunnel barrier layer T of the memory element M is broken, and theresistance state of the memory element M becomes the resistance stateRS. In the memory cell MC to which the ground voltage is applied, theresistance state of the memory element M is maintained to the resistancestate RL. In this manner, the memory circuit 20 writes information tothe selected memory cell MC.

In addition, the controller 22 of the memory circuit 20 controls theoperations of the word line driver 21 and the plurality of readerwriters IO to read information from the memory cell MC of the pluralityof memory cell arrays MA, on the basis of the read command supplied fromthe processing circuit 11. In the read operation, the word line driver21 selects one of the plurality of word lines WL, on the basis of thecommand from the controller 22. In each of the plurality of readerwriters IO, the column switch 31 selects one of the plurality of bitlines BL and couples the selected bit line BL to the sense amplifier 33,and places other bit lines into the floating state, on the basis of thecommand from the controller 22. The sense amplifier 33 generates theread voltage Vread to be applied to the selected bit line BL, on thebasis of the command from the controller 22. The driver 34 drives thevoltage line VL, on the basis of the command from the controller 22.Further, the sense amplifier 33 reads information stored in the memorycell MC, on the basis of the current flowing through the selected bitline BL. Thus, the memory circuit 20 selects the memory cell MC in eachof the plurality of memory cell arrays MA by selecting the word line WLand the bit line BL, and reads information stored in the selected memorycell MC.

(Detailed Operation)

FIG. 5 illustrates an example of the write operation in the memorycircuit 20. In this example, the controller 22 controls the operationsof the word line driver 21 and the plurality of reader writers IO toselect a certain memory cell MC (a memory cell MC1) of the plurality ofmemory cells MC in each of the plurality of memory cell arrays MA, onthe basis of the write command and the write data supplied from theprocessing circuit 11 (FIG. 1).

The word line driver 21 selects one of the plurality of word lines WL,on the basis of the command from the controller 22. Specifically, theword line driver 21 sets a voltage VWL of the word line WL relating tothe memory cell MC1 among the plurality of word lines WL to 1.1 V(VWL=1.1 V), and sets the voltage VWL of other word lines WL to 0 V(VWL=0 V). In FIG. 5, the selected word line WL is indicated by a thickline. Thus, the transistors TRC of the plurality of memory cells MCcorresponding to one row that are coupled to the selected word line WLare set to an ON state.

In the reader writer IO, the column switch 31 selects the bit line BLrelating to the memory cell MC1 among the plurality of bit lines BL andcouples the selected bit line BL to the voltage generator 32, on thebasis of the command from the controller 22. In FIG. 5, the selected bitline BL is indicated by a thick line. The voltage generator 32 generatesthe blow voltage in this example, on the basis of the command from thecontroller 22. In this example, the blow voltage is 1.1 V. Thus, thereader writer 10 sets a voltage VBL of the selected bit line BL to 1.1 V(VBL=1.1 V). In addition, the reader writer 10 places the bit lines BLother than the selected bit line BL among the plurality of bit lines BLinto the floating state. Further, the driver 34 sets a voltage VVL ofthe voltage line VL to 1.1 V (VVL=1.1 V), on the basis of the commandfrom the controller 22.

Accordingly, a blow current Iblow flows from the voltage generator 32through the bit line BL to the memory cell MC1. In the memory cell MC1,the blow current Iblow flows in the order of the bit line BL, the memoryelement M, the transistor TRC, and the source line SL.

In the memory cell MC1, the blow voltage (1.1 V) applied to the bit lineBL is subjected to a voltage division by the resistance value of thememory element M and an ON resistance of the transistor TRC to generatea voltage at the node N1. Because 1.1 V is applied to the drain of thetransistor TRA (a transistor TRA1) associated with the memory cell MC1,a voltage of the source of the transistor TRA1 becomes higher than 0 V.Thus, a voltage of the back gate of the transistor TRC of the memorycell MC1 becomes higher, so that the ON resistance of the transistor TRCbecomes lower. The blow current Iblow becomes easier to flow as the ONresistance of the transistor TRC becomes lower in this manner.Accordingly, the tunnel barrier layer T of the memory element M isbroken and the resistance state of the memory element M becomes theresistance state RS, allowing information to be stored in the memorycell MC1.

In this example, the voltage generator 32 generates the blow voltage onthe basis of the command from the controller 22. However, in a casewhere the voltage generator 32 generates the ground voltage, the readerwriter IO sets the voltage VBL of the selected bit line BL to 0 V. Inthis case, the tunnel barrier layer T of the memory element M is notbroken because no blow current Iblow flows to the memory cell MC1.Accordingly, the resistance state of the memory element M is maintainedto the resistance state RL.

The 32 reader writers IO thus write 32-bit data to the 32 memory cellsMC in the 32 memory cell arrays MA.

FIG. 6 illustrates an example of the read operation in the memorycircuit 20. In this example, the controller 22 controls the operationsof the word line driver 21 and the plurality of reader writers 10 toselect a certain memory cell MC (a memory cell MC2) of the plurality ofmemory cells MC in each of the plurality of memory cell arrays MA, onthe basis of the read command supplied from the processing circuit 11(FIG. 1).

The word line driver 21 selects one of the plurality of word lines WL,on the basis of the command from the controller 22. Specifically, theword line driver 21 sets the voltage VWL of the word line WL relating tothe memory cell MC2 among the plurality of word lines WL to 1.1 V(VWL=1.1 V), and sets the voltage VWL of other word lines WL to 0 V(VWL=0 V). Thus, the transistors TRC of the plurality of memory cells MCcorresponding to one row that are coupled to the selected word line WLare set to the ON state.

In the reader writer TO, the column switch 31 selects the bit line BLrelating to the memory cell MC1 among the plurality of bit lines BL andcouples the selected bit line BL to the sense amplifier 33, on the basisof the command from the controller 22. The sense amplifier 33 generatesthe read voltage Vread, on the basis of the command from the controller22. Thus, the reader writer IO sets the voltage VBL of the selected bitline BL to the read voltage Vread (VBL=Vread). In addition, the readerwriter IO places the bit lines BL other than the selected bit line BLamong the plurality of bit lines BL into the floating state. Further,the driver 34 sets the voltage VVL of the voltage line VL to 1.1 V(VVL=1.1 V), on the basis of the command from the controller 22.

Accordingly, a read current Iread flows from the sense amplifier 33through the bit line BL to the memory cell MC2. In the memory cell MC2,the read current Iread flows in the order of the bit line BL, the memoryelement M, the transistor TRC, and the source line SL.

In the memory cell MC2, the read voltage Vread applied to the bit lineBL is subjected to a voltage division by the resistance value of thememory element M and the ON resistance of the transistor TRC to generatea voltage at the node N1. Because 1.1 V is applied to the drain of thetransistor TRA (a transistor TRA2) associated with the memory cell MC2,a voltage of the source of the transistor TRA2 becomes higher than 0 V.Thus, a voltage of the back gate of the transistor TRC of the memorycell MC2 becomes higher, so that the ON resistance of the transistor TRCbecomes lower. In a case where the ON resistance of the transistor TRCthus becomes lower, the read current Iread more reflects the resistancestate of the memory element M. On the basis of the read current Iread,the sense amplifier 33 reads information stored in the memory cell MC2by determining whether the resistance state of the memory element M isthe resistance state RL or the resistance state RS.

The 32 reader writers IO thus read 32-bit data from the 32 memory cellsMC in the 32 memory cell arrays MA.

As described above, in the semiconductor circuit 1, the transistor TRAis provided, the gate of the transistor TRA is coupled to the other endof the memory element M and the drain of the transistor TRC, and thesource of the transistor TRA is coupled to the back gate of thetransistor TRC. Thus, it is possible to control the voltage of the backgate of the transistor TRC. Hence, it is possible to lower the ONresistance of the transistor TRC.

By reducing the ON resistance of the transistor TRC in this way, it ispossible, for example, in the write operation, to make the blow currentIblow easier to flow and to make the tunnel barrier layer T of thememory element M easier to be broken. Hence, it is possible to widen aso-called blow margin in the semiconductor circuit 1.

In particular, as a miniaturization progresses in a manufacturingprocess, variations in the resistance value of the memory element M canmake the memory element M difficult to be broken. Specifically, ingeneral, it becomes difficult to break the memory element M in a casewhere the resistance value in the resistance state RL of the memoryelement M is low. In the semiconductor circuit 1, the voltage of thenode N1 may become high in a case where the resistance value in theresistance state RL of the memory element M is low. In this case, thevoltage of the gate of the transistor TRA becomes high and the voltageof the back gate of the transistor TRC becomes high, making it possibleto lower the ON resistance of the transistor TRC. Thus, it is possibleto make the blow current Iblow easier to flow and to make the tunnelbarrier layer T of the memory element M easier to be broken.

In addition, because it is possible to lower the ON resistance of thetransistor TRC in this manner, it is possible to reduce a size of thetransistor TRC. In general, the ON resistance of the transistor TRC isincreased in a case where the size of the transistor TRC is reduced,making it difficult to break the memory element M. In the semiconductorcircuit 1, the voltage of the node N1 may become high as the ONresistance of the transistor TRC becomes high. The voltage of the backgate of the transistor TRC becomes high in a case where the voltage ofthe node N1 becomes high in this manner, making it possible to lower theON resistance of the transistor TRC and making it easier to break thememory element M. As described above, in the semiconductor circuit 1, itis possible to reduce the size of the transistor TRC and thereby toreduce the size of the memory cell MC.

In addition, because it is possible to lower the ON resistance of thetransistor TRC in this manner, it is possible, for example, in the writeoperation, to lower the blow voltage. That is, for example, in a casewhere the ON resistance of the transistor TRC is high, a high blowvoltage can be used to break the memory element M more reliably. In sucha case, for example, a high voltage is applied to the transistor TRC,which can lower the reliability of the transistor TRC. In contrast, inthe semiconductor circuit 1, it is possible to lower the blow voltageand thereby to reduce a possibility that the reliability of thetransistor TRC is lowered. In addition, in the semiconductor circuit 1,it is not necessary to provide a charge pump circuit or the like thatgenerates a high blow voltage, allowing the size of the memory circuit20 to be reduced.

In addition, by reducing the ON resistance of the transistor TRC, forexample, in the read operation, the read current tread more reflects theresistance state of the memory element M. Thus, it makes it easier todetermine whether the resistance state of the memory element M is theresistance state RL or the resistance state RS on the basis of the readcurrent tread. Hence, it is possible to widen a so-called read margin.

In addition, in the semiconductor circuit 1, one transistor TRA isprovided for the plurality of memory cells MC corresponding to one row.Thus, it is possible to suppress the number of elements as comparedwith, for example, a case where one transistor TRA is provided for onememory cell MC. Hence, it is possible to reduce the size of the memorycircuit 20.

In addition, in the semiconductor circuit 1, the plurality oftransistors TRC in the plurality of memory cells MC corresponding to onerow is formed on one P-well. Hence, for example, it is possible toreduce the size of the memory circuit 20 as compared with a case wherethe plurality of transistors TRC is respectively formed on the pluralityof P-wells.

In addition, in the semiconductor circuit 1, the memory element M havingthe same configuration as the memory element M of the memory circuit 12is used to configure the memory circuit 20. Thus, it is possible to formthe memory circuit 12 configured to rewrite information and the memorycircuit 20 configured to write information once in the samemanufacturing process. Hence, it is possible to perform manufacturing ina simple method and reduce manufacturing costs.

[Effects]

As described above, in the present embodiment, the transistor TRA isprovided, the gate of the transistor TRA is coupled to the other end ofthe memory element M and the drain of the transistor TRC, and the sourceof the transistor TRA is coupled to the back gate of the transistor TRC.Thus, it is possible to lower the ON resistance of the transistor TRC.Hence, for example, it is possible to reduce the size of the memory celland to reduce the possibility that the reliability is lowered.Accordingly, for example, it is possible to widen the blow margin andwiden the read margin.

Modification Example 1

In the embodiment described above, the driver 34 sets the voltage VVL ofthe voltage line VL to 1.1 V in the read operation, as illustrated inFIG. 6. However, it is not limited thereto. Alternatively, for example,the voltage VVL of voltage line VL may be set to 0 V.

Modification Example 2

In the embodiment described above, one source line SL is provided forthe plurality of memory cells MC corresponding to one column. However,it is not limited thereto. Alternatively, for example, one source lineSL may be provided for the plurality of memory cells MC corresponding totwo columns, as in a memory circuit 20A illustrated in FIG. 7. In thisexample, the plurality of memory cells MC in the first column and theplurality of memory cells MC in the second column are coupled to onesource line SL. Further, the plurality of memory cells MC in the thirdcolumn and the plurality of memory cells MC in the fourth column arecoupled to one source line SL. This applies similarly to the fifth andsubsequent columns.

Modification Example 3

In the embodiment described above, one bit information is stored in onememory cell MC. However, it is not limited thereto. One bit informationmay be stored in two memory cells MC. Hereinafter, a semiconductorcircuit 1C according to the present modification example will bedescribed in detail. The semiconductor circuit 1C includes a memorycircuit 40.

FIG. 8 illustrates a configuration example of the memory cell array MAand the reader writer IO according to the memory circuit 40. In thememory cell array MA, two memory cells MC coupled to the same word lineWL structure a memory cell pair MCP. In this example, for example, thememory cell MC in the first column and the memory cell MC in the secondcolumn structure the memory cell pair MCP, and the memory cell MC in thethird column and the memory cell MC in the fourth column structure thememory cell pair MCP. This applies similarly to the fifth and subsequentcolumns. Similarly, the two bit lines BL structure a bit line pair BLP.Specifically, the first bit line BL and the second bit line BL structurethe bit line pair BLP, and the third bit line BL and the fourth bit lineBL structure the bit line pair BLP. This applies similarly to the fifthand subsequent bit lines.

In the memory circuit 40, after the write operation, the resistancestate of the memory element M of the left side memory cell MC in thememory cell pair MCP is different from the resistance state of thememory element of the right side memory cell MC. Specifically, in a casewhere the resistance state of the memory element M of the left sidememory cell MC is the resistance state RS, the resistance state of thememory element M of the right side memory cell MC is the resistancestate RL. In a case where the resistance state of the memory element Mof the left side memory cell MC is the resistance state RL, theresistance state of the memory element M of the right side memory cellMC is the resistance state RS. In this manner, the memory cell pair MCPstores one-bit information.

The reader writer IO includes a column switch 41, a voltage generator42, and a sense amplifier 43.

The column switch 41 is configured to, in the write operation, selectone of the plurality of bit line pairs BLP and couple the selected bitline pair BLP to the voltage generator 42, and place each of the bitlines BL of other bit line pairs BLP into the floating state, on thebasis of the command from the controller 22. Further, the column switch41 is configured to, in the read operation, select one of the pluralityof bit line pairs BLP and couple the selected bit line pair BLP to thesense amplifier 43, and place each of the bit lines BL of other bit linepairs BLP into the floating state, on the basis of the command from thecontroller 22.

The voltage generator 42 is configured to, in the write operation,generate the ground voltage and the blow voltage to be applied to eachof the bit lines BL of the selected bit line pair BLP, on the basis ofthe command from the controller 22.

The sense amplifier 43 is configured to, in the read operation, generatethe read voltage Vread to be applied to each of the bit lines BL of theselected bit line pair BLP and read information stored in the memorycell pair MCP on the basis of a current flowing through each of the bitlines BL of the selected bit line pair BLP, on the basis of the commandfrom the controller 22.

FIG. 9 illustrates an example of the write operation in the memorycircuit 40. In this example, the controller 22 controls the operationsof the word line driver 21 and the plurality of reader writers IO toselect a certain memory cell pair MCP (a memory cell pair MCP1) of theplurality of memory cell pairs MCP in each of the plurality of memorycell arrays MA, on the basis of the write command and the write datasupplied from the processing circuit 11.

The word line driver 21 selects one of the plurality of word lines WL,on the basis of the command from the controller 22. Specifically, theword line driver 21 sets the voltage VWL of the word line WL relating tothe memory cell pair MCP1 among the plurality of word lines WL to 1.1 V(VWL=1.1 V), and sets the voltage VWL of other word lines WL to 0 V(VWL=0 V). Thus, the transistors TRC of the plurality of memory cells MCcorresponding to one row that are coupled to the selected word line WLare set to the ON state.

In the reader writer IO, the column switch 41 selects the bit line pairBLP relating to the memory cell pair MCP1 among the plurality of bitline pairs BLP and couples two bit lines BL of the selected bit linepair BLP to the voltage generator 42, on the basis of the command fromthe controller 22. The voltage generator 42 generates the ground voltage(0 V) and the blow voltage (1.1 V in this example), on the basis of thecommand from the controller 22. Thus, in this example, the reader writer10 sets the voltage VBL of the left side bit line BL to 1.1 V (VBL=1.1V) and the voltage VBL of the right side bit line BL to 0V (VBL=0 V),out of the two bit lines BL of the selected bit line pair BLP. Inaddition, the reader writer 10 places the bit lines BL other than thebit lines BL of the selected bit line pair BLP among the plurality ofbit lines BL into the floating state. Further, the driver 34 sets thevoltage VVL of the voltage line VL to 1.1 V (VVL=1.1 V), on the basis ofthe command from the controller 22.

Accordingly, the blow current Iblow flows from the voltage generator 42through the left side bit line BL of the selected bit line pair BLP tothe left side memory cell MC (a memory cell MC3) of the memory cell pairMCP1. In the memory cell MC3, the blow current Iblow flows in the orderof the bit line BL, the memory element M, the transistor TRC, and thesource line SL. The transistor TRA (a transistor TRA3) associated withthe memory cell pair MCP1 raises the voltage of the back gate of thetransistor TRC of the memory cell MC3 so that the ON resistance of thetransistor TRC becomes lower, making it easier for the blow currentIblow to flow. Thus, the resistance state of the memory element M of thememory cell MC3 becomes the resistance state RS. On the other hand,because no blow current Iblow flows to the right side memory cell MC (amemory cell MC4) of the memory cell pair MCP1, the tunnel barrier layerT of the memory element M is not broken. Accordingly, the resistancestate of the memory element M of the memory cell MC4 is maintained tothe resistance state RL. In this manner, information is stored in thememory cell pair MCP1.

Note that, in this example, the reader writer IO sets the voltage VBL ofthe left side bit line BL to 1.1 V (VBL=1.1 V) and the voltage VBL ofthe right side bit line BL to 0 V (VBL=0 V), out of the two bit lines BLof the selected bit line pair BLP. Alternatively, in a case where thereader writer IO sets the voltage VBL of the left side bit line BL to 0V (VBL=0 V) and the voltage VBL of the right side bit line BL to 1.1 V(VBL=1.1 V), the resistance state of the memory element M of the memorycell MC4 becomes the resistance state RS, and the resistance state ofthe memory element M of the memory cell MC3 is maintained to theresistance state RL.

The 32 reader writers IO thus write 32-bit data to the 32 memory cellpairs MCP in the 32 memory cell arrays MA.

FIG. 10 illustrates an example of the read operation in the memorycircuit 40. In this example, the controller 22 controls the operationsof the word line driver 21 and the plurality of reader writers IO toselect a certain memory cell pair MCP (a memory cell pair MCP2) of theplurality of memory cell pairs MCP in each of the plurality of memorycell arrays MA, on the basis of the read command supplied from theprocessing circuit 11.

The word line driver 21 selects one of the plurality of word lines WL,on the basis of the command from the controller 22. Specifically, theword line driver 21 sets the voltage VWL of the word line WL relating tothe memory cell pair MCP2 among the plurality of word lines WL to 1.1 V(VWL=1.1 V), and sets the voltage VWL of other word lines WL to 0 V(VWL=0 V). Thus, the transistors TRC of the plurality of memory cells MCcorresponding to one row that are coupled to the selected word line WLare set to the ON state.

In the reader writer IO, the column switch 41 selects the bit line pairBLP relating to the memory cell pair MCP2 among the plurality of bitline pairs BLP and couples two bit lines BL of the selected bit linepair BLP to the sense amplifier 43, on the basis of the command from thecontroller 22. The sense amplifier 43 generates the read voltage Vread,on the basis of the command from the controller 22. Thus, the readerwriter IO sets the voltage VBL of the two bit lines BL of the selectedbit line pair BLP to the read voltage Vread (VBL=Vread). In addition,the reader writer IO places the bit lines BL other than the bit lines BLof the selected bit line pair BLP among the plurality of bit lines BLinto the floating state. Further, the driver 34 sets the voltage VVL ofthe voltage line VL to 1.1 V (VVL=1.1 V), on the basis of the commandfrom the controller 22.

Accordingly, from the sense amplifier 43, a read current Iread5 flowsthrough the left side bit line BL of the selected bit line pair BLP tothe left side memory cell MC (a memory cell MC5) of the memory cell pairMCP2, and a read current Iread6 flows through the right side bit line BLof the selected bit line pair BLP to the right side memory cell MC (amemory cell MC6) of the memory cell pair MCP2. The transistor TRA (atransistor TRA4) associated with the memory cell pair MCP2 raises thevoltage of the back gates of the transistors TRC of the memory cells MC5and MC6, so that the ON resistance of the transistors TRC of the memorycells MC5 and MC6 becomes lower. Thus, the read current Iread5 morereflects the resistance state of the memory element M of the memory cellMC5, and the read current Iread6 more reflects the resistance state ofthe memory element M of the memory cell MC6. On the basis of the readcurrents Iread5 and Iread6, the sense amplifier 33 reads informationstored in the memory cell pair MCP2, for example, by determining whichof the resistance value of the memory element M of the memory cell MC5and the resistance value of the memory element M of the memory cell MC6is greater.

The 32 reader writers IO thus read 32-bit data from the 32 memory cellpairs MCP in the 32 memory cell arrays MA.

As described above, although the present modification example is appliedto the memory circuit 20 (FIG. 3) according to the embodiment describedabove, it is not limited thereto. For example, as illustrated in FIG.11, the present modification example may be applied to the memorycircuit 20A (FIG. 7) according to the modification example 2.

Modification Example 4

Although the source lines SL are grounded in the embodiment describedabove, it is not limited thereto. The source lines SL may be selectivelydriven. Hereinafter, a semiconductor circuit 1D according to the presentmodification example will be described in detail. The semiconductorcircuit 1D includes a memory circuit 50.

FIG. 12 illustrates a configuration example of the memory circuit 50.The memory circuit 50 has the plurality of memory cell arrays MA (32memory cell arrays MA[0], MA[1], . . . , MA[31], in this example), theplurality of reader writers IO (32 reader writers IO[0], . . . , IO[31],in this example), a plurality of source line drivers DRV (32 source linedrivers DRV[0], DRV[1], DRV[31], in this example), the word line driver21, and a controller 52. The plurality of source line drivers DRV isrespectively provided corresponding to the plurality of memory cellarrays MA.

FIG. 13 illustrates a configuration example of the source line driverDRV. In FIG. 13, the memory cell array MA, the reader writer IO, and theword line driver 21 are also depicted for convenience of explanation.The source line driver DRV is configured to drive the plurality ofsource lines SL on the basis of a command from the controller 52. Thesource line driver DRV has a column switch 61 and a voltage generator62.

The column switch 61 is configured to, in the write operation and theread operation, select one of the plurality of source lines SL andcouple the selected source line SL to the voltage generator 62, andplace other source lines SL into the floating state, on the basis of thecommand from the controller 52. The column switches 61 of the pluralityof source line drivers DRV are adapted to select the source lines SLthat are the same as each other in number of order, on the basis of thecommand from the controller 52.

The voltage generator 62 is configured to, in the write operation andthe read operation, generate the ground voltage to be applied to theselected source line SL, on the basis of the command from the controller52.

The controller 52 (FIG. 12) is configured to control operations of theword line driver 21, the plurality of source line drivers DRV, and theplurality of reader writers 10 to write information to the memory cellMC of the plurality of memory cell arrays MA, on the basis of the writecommand and the write data supplied from the processing circuit 11.Further, the controller 52 is configured to control operations of theword line driver 21, the plurality of source line drivers DRV, and theplurality of reader writers 10 to read information from the memory cellMC of the plurality of memory cell arrays MA, on the basis of the readcommand supplied from the processing circuit 11.

FIG. 14 illustrates an example of the write operation in the memorycircuit 50. In this example, the controller 52 controls the operationsof the word line driver 21, the plurality of source line drivers DRV,and the plurality of reader writers 10 to select a certain memory cellMC (a memory cell MC7) of the plurality of memory cells MC in each ofthe plurality of memory cell arrays MA, on the basis of the writecommand and the write data supplied from the processing circuit 11 (FIG.1).

The word line driver 21 selects one of the plurality of word lines WL,on the basis of the command from the controller 52. Specifically, theword line driver 21 sets the voltage VWL of the word line WL relating tothe memory cell MC7 among the plurality of word lines WL to 1.1 V(VWL=1.1 V), and sets the voltage VWL of other word lines WL to 0 V(VWL=0 V). Thus, the transistors TRC of the plurality of memory cells MCcorresponding to one row that are coupled to the selected word line WLare set to the ON state.

In the source line driver DRV, the column switch 61 selects the sourceline SL relating to the memory cell MC7 among the plurality of sourcelines SL and couples the selected source line SL to the voltagegenerator 62, on the basis of the command from the controller 52. InFIG. 14, the selected source line SL is indicated by a thick line. Thevoltage generator 62 generates the ground voltage in this example, onthe basis of the command from the controller 52. Thus, the source linedriver DRV sets a voltage VSL of the selected source line SL to 0 V(VBL=0 V). In addition, the source line driver DRV places the sourcelines SL other than the selected source line SL among the plurality ofsource lines SL into the floating state.

In the reader writer IO, the column switch 31 selects the bit line BLrelating to the memory cell MC7 among the plurality of bit lines BL andcouples the selected bit line BL to the voltage generator 32, on thebasis of the command from the controller 52. The voltage generator 32generates the blow voltage (in this example, 1.1 V) in this example, onthe basis of the command from the controller 52. Thus, the reader writerIO sets the voltage VBL of the selected bit line BL to 1.1 V (VBL=1.1V). In addition, the reader writer 10 places the bit lines BL other thanthe selected bit line BL among the plurality of bit lines BL into thefloating state. Further, the driver 34 sets the voltage VVL of thevoltage line VL to 1.1 V (VVL=1.1 V), on the basis of the command fromthe controller 52.

Accordingly, the blow current Iblow flows from the voltage generator 32through the bit line BL to the memory cell MC1. In the memory cell MC7,the blow current Iblow flows in the order of the bit line BL, the memoryelement M, the transistor TRC, and the source line SL. The transistorTRA (a transistor TRA7) associated with the memory cell MC7 raises thevoltage of the back gate of the transistor TRC of the memory cell MC7 sothat the ON resistance of the transistor TRC becomes lower, making iteasier for the blow current Iblow to flow. Thus, the resistance state ofthe memory element M of the memory cell MC7 becomes the resistance stateRS.

FIG. 15 illustrates an example of the read operation in the memorycircuit 50. In this example, the controller 52 controls the operationsof the word line driver 21, the plurality of source line drivers DRV,and the plurality of reader writers IO to select a certain memory cellMC (a memory cell MC8) of the plurality of memory cells MC in each ofthe plurality of memory cell arrays MA, on the basis of the read commandsupplied from the processing circuit 11.

The word line driver 21 selects one of the plurality of word lines WL,on the basis of the command from the controller 52. Specifically, theword line driver 21 sets the voltage VWL of the word line WL relating tothe memory cell MC8 among the plurality of word lines WL to 1.1 V(VWL=1.1 V), and sets the voltage VWL of other word lines WL to 0 V(VWL=0 V). Thus, the transistors TRC of the plurality of memory cells MCcorresponding to one row that are coupled to the selected word line WLare set to the ON state.

In the source line driver DRV, the column switch 61 selects the sourceline SL relating to the memory cell MC8 among the plurality of sourcelines SL and couples the selected source line SL to the voltagegenerator 62, on the basis of the command from the controller 52. Thevoltage generator 62 generates the ground voltage in this example, onthe basis of the command from the controller 52. Thus, the source linedriver DRV sets the voltage VSL of the selected source line SL to 0 V(VBL=0 V). In addition, the source line driver DRV places the sourcelines SL other than the selected source line SL among the plurality ofsource lines SL into the floating state.

In the reader writer TO, the column switch 31 selects the bit line BLrelating to the memory cell MC8 among the plurality of bit lines BL andcouples the selected bit line BL to the sense amplifier 33, on the basisof the command from the controller 52. The sense amplifier 33 generatesthe read voltage Vread, on the basis of the command from the controller52. Thus, the reader writer IO sets the voltage VBL of the selected bitline BL to the read voltage Vread (VBL=Vread). In addition, the readerwriter IO places the bit lines BL other than the selected bit line BLamong the plurality of bit lines BL into the floating state. Further,the driver 34 sets the voltage VVL of the voltage line VL to 1.1 V(VVL=1.1 V), on the basis of the command from the controller 52.

Accordingly, the read current Iread flows from the sense amplifier 33through the bit line BL to the memory cell MC8. In the memory cell MC8,the read current Iread flows in the order of the bit line BL, the memoryelement M, the transistor TRC, and the source line SL. The transistorTRA (a transistor TRA8) associated with the memory cell MC8 raises thevoltage of the back gate of the transistor TRC of the memory cell MC8,so that the ON resistance of the transistor TRC becomes lower. Thus, theread current Iread more reflects the resistance state of the memoryelement M of the memory cell MC8. On the basis of the read currentIread, the sense amplifier 33 reads information stored in the memorycell MC8 by determining whether the resistance state of the memoryelement M is the resistance state RL or the resistance state RS.

As described above, although the memory circuit 20 (FIG. 3) according tothe embodiment described above is applied to the present modificationexample, it is not limited thereto. For example, as illustrated in FIG.16, the present modification example may be applied to the memorycircuit 20A (FIG. 7) according to the modification example 2. The sourceline driver DRV has a column switch 71. The column switch 71 isconfigured to, in the write operation and the read operation, select oneof the plurality of source lines SL and couple the selected source lineSL to the voltage generator 62, and place other source lines SL into thefloating state, on the basis of the command from the controller 52.

OTHER MODIFICATION EXAMPLES

In addition, two or more of the modification examples described abovemay be combined.

2. Application Example

Next, an application example of a technique described in the aboveembodiment and modification examples to an electronic apparatus will bedescribed.

FIG. 17 illustrates an external appearance of a smartphone to which thesemiconductor circuit of the above embodiment or the like is applied.The smartphone includes, for example, a body section 310 and a displaysection 320. It is possible to apply the semiconductor circuit of theabove embodiment or the like to an electronic apparatus in variousfields, such as a digital camera, a notebook personal computer, aportable gaming machine, a video camera, and the like, in addition tothe smartphone.

Although the present technology has been described above with referenceto the embodiment, the modification examples, and the applicationexample to the electronic apparatus, the present technology is notlimited to the embodiment and the like, and various modifications can bemade.

For example, in each of the embodiments described above, the transistorsTRC and TRA are each configured using the N-type MOS transistor.However, it is not limited thereto. Alternatively, for example, a P-typeMOS transistor may be used to configure the transistors TRC and TRA.

It is to be noted that the effects described in the presentspecification are merely illustrative and non-limiting, and othereffects may be provided.

It should be noted that the present technology may be configured asbelow. According to the present technology having the followingconfiguration, it is possible to reduce a size of a memory cell.

(1) A semiconductor circuit including:

a first memory element including a first terminal, a second terminalcoupled to a first node, and a tunnel barrier film, and configured tostore information by breaking the tunnel barrier film;

a first transistor including a drain coupled to the first node, asource, a gate, and a back gate coupled to a second node; and

a second transistor including a drain, a source coupled to the secondnode, and a gate coupled to the first node.

(2) The semiconductor circuit according to (1), further including adriver configured to perform a first operation that causes the firstmemory element to store the information, by applying a reference voltageto the source of the first transistor, applying a first voltage that isdifferent from the reference voltage to the gate of the firsttransistor, applying a second voltage that is different from thereference voltage to the first terminal of the first memory element, andapplying a third voltage that is different from the reference voltage tothe drain of the second transistor.(3) The semiconductor circuit according to (2), in which the driver isfurther configured to perform a second operation that reads theinformation from the first memory element, by applying the referencevoltage to the source of the first transistor, applying the firstvoltage to the gate of the first transistor, and applying a fourthvoltage that is different from the reference voltage to the firstterminal of the first memory element.(4) The semiconductor circuit according to (3), in which a differencevoltage between the fourth voltage and the reference voltage is lowerthan a difference voltage between the second voltage and the referencevoltage.(5) The semiconductor circuit according to (3) or (4), in which thedriver is configured to apply the third voltage to the drain of thesecond transistor in the second operation.(6) The semiconductor circuit according to (3) or (4), in which thedriver is configured to apply the reference voltage to the drain of thesecond transistor in the second operation.(7) The semiconductor circuit according to (1), further including:

a second memory element including a first terminal, a second terminalcoupled to the first node, and a tunnel barrier film, and configured tostore information by breaking the tunnel barrier film;

a third transistor including a drain coupled to the first node, asource, a gate, and a back gate coupled to the second node;

a first control line coupled to the gate of the first transistor and thegate of the third transistor;

a second control line coupled to the first terminal of the first memoryelement;

a third control line coupled to the first terminal of the second memoryelement; and

a fourth control line coupled to the drain of the second transistor.

(8) The semiconductor circuit according to (7), further including:

a fifth control line coupled to the source of the first transistor; and

a driver configured to perform a first operation that causes the firstmemory element to store the information, by applying a reference voltageto the fifth control line, applying a first voltage that is differentfrom the reference voltage to the first control line, applying a secondvoltage that is different from the reference voltage to the secondcontrol line, placing the third control line into a floating state, andapplying a third voltage that is different from the reference voltage tothe fourth control line.

(9) The semiconductor circuit according to (8), further including

a sixth control line coupled to the source of the third transistor, inwhich

the driver is configured to apply the reference voltage to the sixthcontrol line in the first operation.

(10) The semiconductor circuit according to (8), further including

a sixth control line coupled to the source of the third transistor, inwhich

the driver is configured to place the sixth control line into thefloating state in the first operation.

(11) The semiconductor circuit according to (8), in which the fifthcontrol line is further coupled to the source of the third transistor.(12) The semiconductor circuit according to any one of (8) to (11), inwhich the driver is further configured to perform a second operationthat reads the information from the first memory element, by applyingthe reference voltage to the fifth control line, applying the firstvoltage to the first control line, applying a fourth voltage that isdifferent from the reference voltage to the second control line, andplacing the third control line into the floating state.(13) The semiconductor circuit according to claim 1, in which the tunnelbarrier film includes a material including MgO or alumina.(14) The semiconductor circuit according to any one of (1) to (13),further including a memory circuit including a magnetic tunnel junctiondevice having a tunnel barrier film.(15) An electronic apparatus including:

a first memory element including a first terminal, a second terminalcoupled to a first node, and a tunnel barrier film, and configured tostore information by breaking the tunnel barrier film;

a first transistor including a drain coupled to the first node, asource, a gate, and a back gate coupled to a second node;

a second transistor including a drain, a source coupled to the secondnode, and a gate coupled to the first node; and

a processing circuit configured to perform a process, on the basis ofthe information stored in the first memory element.

The present application claims the benefit of Japanese Priority PatentApplication JP2019-048576 filed with the Japan Patent Office on Mar. 15,2019, the entire contents of which are incorporated herein by reference.

It should be understood by those skilled in the art that variousmodifications, combinations, sub-combinations and alterations may occurdepending on design requirements and other factors insofar as they arewithin the scope of the appended claims or the equivalents thereof.

1. A semiconductor circuit comprising: a first memory element includinga first terminal, a second terminal coupled to a first node, and atunnel barrier film, and configured to store information by breaking thetunnel barrier film; a first transistor including a drain coupled to thefirst node, a source, a gate, and a back gate coupled to a second node;and a second transistor including a drain, a source coupled to thesecond node, and a gate coupled to the first node.
 2. The semiconductorcircuit according to claim 1, further comprising a driver configured toperform a first operation that causes the first memory element to storethe information, by applying a reference voltage to the source of thefirst transistor, applying a first voltage that is different from thereference voltage to the gate of the first transistor, applying a secondvoltage that is different from the reference voltage to the firstterminal of the first memory element, and applying a third voltage thatis different from the reference voltage to the drain of the secondtransistor.
 3. The semiconductor circuit according to claim 2, whereinthe driver is further configured to perform a second operation thatreads the information from the first memory element, by applying thereference voltage to the source of the first transistor, applying thefirst voltage to the gate of the first transistor, and applying a fourthvoltage that is different from the reference voltage to the firstterminal of the first memory element.
 4. The semiconductor circuitaccording to claim 3, wherein a difference voltage between the fourthvoltage and the reference voltage is lower than a difference voltagebetween the second voltage and the reference voltage.
 5. Thesemiconductor circuit according to claim 3, wherein the driver isconfigured to apply the third voltage to the drain of the secondtransistor in the second operation.
 6. The semiconductor circuitaccording to claim 3, wherein the driver is configured to apply thereference voltage to the drain of the second transistor in the secondoperation.
 7. The semiconductor circuit according to claim 1, furthercomprising: a second memory element including a first terminal, a secondterminal coupled to the first node, and a tunnel barrier film, andconfigured to store information by breaking the tunnel barrier film; athird transistor including a drain coupled to the first node, a source,a gate, and a back gate coupled to the second node; a first control linecoupled to the gate of the first transistor and the gate of the thirdtransistor; a second control line coupled to the first terminal of thefirst memory element; a third control line coupled to the first terminalof the second memory element; and a fourth control line coupled to thedrain of the second transistor.
 8. The semiconductor circuit accordingto claim 7, further comprising: a fifth control line coupled to thesource of the first transistor; and a driver configured to perform afirst operation that causes the first memory element to store theinformation, by applying a reference voltage to the fifth control line,applying a first voltage that is different from the reference voltage tothe first control line, applying a second voltage that is different fromthe reference voltage to the second control line, placing the thirdcontrol line into a floating state, and applying a third voltage that isdifferent from the reference voltage to the fourth control line.
 9. Thesemiconductor circuit according to claim 8, further comprising a sixthcontrol line coupled to the source of the third transistor, wherein thedriver is configured to apply the reference voltage to the sixth controlline in the first operation.
 10. The semiconductor circuit according toclaim 8, further comprising a sixth control line coupled to the sourceof the third transistor, wherein the driver is configured to place thesixth control line into the floating state in the first operation. 11.The semiconductor circuit according to claim 8, wherein the fifthcontrol line is further coupled to the source of the third transistor.12. The semiconductor circuit according to claim 8, wherein the driveris further configured to perform a second operation that reads theinformation from the first memory element, by applying the referencevoltage to the fifth control line, applying the first voltage to thefirst control line, applying a fourth voltage that is different from thereference voltage to the second control line, and placing the thirdcontrol line into the floating state.
 13. The semiconductor circuitaccording to claim 1, wherein the tunnel barrier film includes amaterial comprising MgO or alumina.
 14. The semiconductor circuitaccording to claim 1, further comprising a memory circuit including amagnetic tunnel junction device having a tunnel barrier film.
 15. Anelectronic apparatus comprising: a first memory element including afirst terminal, a second terminal coupled to a first node, and a tunnelbarrier film, and configured to store information by breaking the tunnelbarrier film; a first transistor including a drain coupled to the firstnode, a source, a gate, and a back gate coupled to a second node; asecond transistor including a drain, a source coupled to the secondnode, and a gate coupled to the first node; and a processing circuitconfigured to perform a process, on a basis of the information stored inthe first memory element.